Struct stm32f4xx_hal::pac::rcc::RegisterBlock

source · [−]
pub struct RegisterBlock {
Show 21 fields
    pub cr: Reg<CR_SPEC>,
    pub pllcfgr: Reg<PLLCFGR_SPEC>,
    pub cfgr: Reg<CFGR_SPEC>,
    pub cir: Reg<CIR_SPEC>,
    pub ahb1rstr: Reg<AHB1RSTR_SPEC>,
    pub ahb2rstr: Reg<AHB2RSTR_SPEC>,
    pub apb1rstr: Reg<APB1RSTR_SPEC>,
    pub apb2rstr: Reg<APB2RSTR_SPEC>,
    pub ahb1enr: Reg<AHB1ENR_SPEC>,
    pub ahb2enr: Reg<AHB2ENR_SPEC>,
    pub apb1enr: Reg<APB1ENR_SPEC>,
    pub apb2enr: Reg<APB2ENR_SPEC>,
    pub ahb1lpenr: Reg<AHB1LPENR_SPEC>,
    pub ahb2lpenr: Reg<AHB2LPENR_SPEC>,
    pub apb1lpenr: Reg<APB1LPENR_SPEC>,
    pub apb2lpenr: Reg<APB2LPENR_SPEC>,
    pub bdcr: Reg<BDCR_SPEC>,
    pub csr: Reg<CSR_SPEC>,
    pub sscgr: Reg<SSCGR_SPEC>,
    pub plli2scfgr: Reg<PLLI2SCFGR_SPEC>,
    pub dckcfgr: Reg<DCKCFGR_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields

cr: Reg<CR_SPEC>

0x00 - clock control register

pllcfgr: Reg<PLLCFGR_SPEC>

0x04 - PLL configuration register

cfgr: Reg<CFGR_SPEC>

0x08 - clock configuration register

cir: Reg<CIR_SPEC>

0x0c - clock interrupt register

ahb1rstr: Reg<AHB1RSTR_SPEC>

0x10 - AHB1 peripheral reset register

ahb2rstr: Reg<AHB2RSTR_SPEC>

0x14 - AHB2 peripheral reset register

apb1rstr: Reg<APB1RSTR_SPEC>

0x20 - APB1 peripheral reset register

apb2rstr: Reg<APB2RSTR_SPEC>

0x24 - APB2 peripheral reset register

ahb1enr: Reg<AHB1ENR_SPEC>

0x30 - AHB1 peripheral clock register

ahb2enr: Reg<AHB2ENR_SPEC>

0x34 - AHB2 peripheral clock enable register

apb1enr: Reg<APB1ENR_SPEC>

0x40 - APB1 peripheral clock enable register

apb2enr: Reg<APB2ENR_SPEC>

0x44 - APB2 peripheral clock enable register

ahb1lpenr: Reg<AHB1LPENR_SPEC>

0x50 - AHB1 peripheral clock enable in low power mode register

ahb2lpenr: Reg<AHB2LPENR_SPEC>

0x54 - AHB2 peripheral clock enable in low power mode register

apb1lpenr: Reg<APB1LPENR_SPEC>

0x60 - APB1 peripheral clock enable in low power mode register

apb2lpenr: Reg<APB2LPENR_SPEC>

0x64 - APB2 peripheral clock enabled in low power mode register

bdcr: Reg<BDCR_SPEC>

0x70 - Backup domain control register

csr: Reg<CSR_SPEC>

0x74 - clock control & status register

sscgr: Reg<SSCGR_SPEC>

0x80 - spread spectrum clock generation register

plli2scfgr: Reg<PLLI2SCFGR_SPEC>

0x84 - PLLI2S configuration register

dckcfgr: Reg<DCKCFGR_SPEC>

0x8c - RCC Dedicated Clock Configuration Register

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