☰
CCR4
Trait Implementations
DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral>
DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory>
DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral>
DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory>
DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral>
DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory>
DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral>
DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory>
DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral>
DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory>
DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral>
DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory>
In stm32f4xx_hal::timer
?
Type Definition
stm32f4xx_hal
::
timer
::
CCR4
source
·
[
−
]
pub type CCR4<T> =
CCR
<T, 3>;
Trait Implementations
source
impl
DMASet
<
StreamX
<
DMA1
, 1>, 6,
MemoryToPeripheral
> for
CCR4
<
TIM5
>
source
impl
DMASet
<
StreamX
<
DMA1
, 1>, 6,
PeripheralToMemory
> for
CCR4
<
TIM5
>
source
impl
DMASet
<
StreamX
<
DMA1
, 2>, 5,
MemoryToPeripheral
> for
CCR4
<
TIM3
>
source
impl
DMASet
<
StreamX
<
DMA1
, 2>, 5,
PeripheralToMemory
> for
CCR4
<
TIM3
>
source
impl
DMASet
<
StreamX
<
DMA1
, 3>, 6,
MemoryToPeripheral
> for
CCR4
<
TIM5
>
source
impl
DMASet
<
StreamX
<
DMA1
, 3>, 6,
PeripheralToMemory
> for
CCR4
<
TIM5
>
source
impl
DMASet
<
StreamX
<
DMA1
, 6>, 3,
MemoryToPeripheral
> for
CCR4
<
TIM2
>
source
impl
DMASet
<
StreamX
<
DMA1
, 6>, 3,
PeripheralToMemory
> for
CCR4
<
TIM2
>
source
impl
DMASet
<
StreamX
<
DMA1
, 7>, 3,
MemoryToPeripheral
> for
CCR4
<
TIM2
>
source
impl
DMASet
<
StreamX
<
DMA1
, 7>, 3,
PeripheralToMemory
> for
CCR4
<
TIM2
>
source
impl
DMASet
<
StreamX
<
DMA2
, 4>, 6,
MemoryToPeripheral
> for
CCR4
<
TIM1
>
source
impl
DMASet
<
StreamX
<
DMA2
, 4>, 6,
PeripheralToMemory
> for
CCR4
<
TIM1
>