Trait stm32f4xx_hal::dma::traits::DMASet

pub unsafe trait DMASet<STREAM, const CHANNEL: u8, DIRECTION> { }

Trait to mark a set of Stream, Channel and Direction for a Peripheral as correct together.

Safety

Memory corruption might occur if this trait is implemented for an invalid combination.

Implementors

impl DMASet<StreamX<DMA1, 0>, 0, PeripheralToMemory> for SPI3

impl DMASet<StreamX<DMA1, 0>, 0, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<SPI3>

impl DMASet<StreamX<DMA1, 0>, 1, PeripheralToMemory> for stm32f4xx_hal::i2c::dma::Rx<I2C1>

impl DMASet<StreamX<DMA1, 0>, 1, PeripheralToMemory> for I2C1

impl DMASet<StreamX<DMA1, 0>, 2, MemoryToPeripheral> for CCR1<TIM4>

impl DMASet<StreamX<DMA1, 0>, 2, PeripheralToMemory> for CCR1<TIM4>

impl DMASet<StreamX<DMA1, 0>, 6, MemoryToPeripheral> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 0>, 6, MemoryToPeripheral> for CCR3<TIM5>

impl DMASet<StreamX<DMA1, 0>, 6, PeripheralToMemory> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 0>, 6, PeripheralToMemory> for CCR3<TIM5>

impl DMASet<StreamX<DMA1, 1>, 1, PeripheralToMemory> for stm32f4xx_hal::i2c::dma::Rx<I2C3>

impl DMASet<StreamX<DMA1, 1>, 1, PeripheralToMemory> for I2C3

impl DMASet<StreamX<DMA1, 1>, 3, MemoryToPeripheral> for DMAR<TIM2>

impl DMASet<StreamX<DMA1, 1>, 3, MemoryToPeripheral> for CCR3<TIM2>

impl DMASet<StreamX<DMA1, 1>, 3, PeripheralToMemory> for DMAR<TIM2>

impl DMASet<StreamX<DMA1, 1>, 3, PeripheralToMemory> for CCR3<TIM2>

impl DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 1>, 6, MemoryToPeripheral> for CCR4<TIM5>

impl DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 1>, 6, PeripheralToMemory> for CCR4<TIM5>

impl DMASet<StreamX<DMA1, 2>, 0, PeripheralToMemory> for SPI3

impl DMASet<StreamX<DMA1, 2>, 0, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<SPI3>

impl DMASet<StreamX<DMA1, 2>, 3, PeripheralToMemory> for stm32f4xx_hal::i2c::dma::Rx<I2C3>

impl DMASet<StreamX<DMA1, 2>, 3, PeripheralToMemory> for I2C3

impl DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral> for DMAR<TIM3>

impl DMASet<StreamX<DMA1, 2>, 5, MemoryToPeripheral> for CCR4<TIM3>

impl DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory> for DMAR<TIM3>

impl DMASet<StreamX<DMA1, 2>, 5, PeripheralToMemory> for CCR4<TIM3>

impl DMASet<StreamX<DMA1, 2>, 6, MemoryToPeripheral> for CCR1<TIM5>

impl DMASet<StreamX<DMA1, 2>, 6, PeripheralToMemory> for CCR1<TIM5>

impl DMASet<StreamX<DMA1, 2>, 7, PeripheralToMemory> for stm32f4xx_hal::i2c::dma::Rx<I2C2>

impl DMASet<StreamX<DMA1, 2>, 7, PeripheralToMemory> for I2C2

impl DMASet<StreamX<DMA1, 3>, 0, PeripheralToMemory> for SPI2

impl DMASet<StreamX<DMA1, 3>, 0, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<SPI2>

impl DMASet<StreamX<DMA1, 3>, 2, MemoryToPeripheral> for CCR2<TIM4>

impl DMASet<StreamX<DMA1, 3>, 2, PeripheralToMemory> for CCR2<TIM4>

impl DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 3>, 6, MemoryToPeripheral> for CCR4<TIM5>

impl DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 3>, 6, PeripheralToMemory> for CCR4<TIM5>

impl DMASet<StreamX<DMA1, 3>, 7, PeripheralToMemory> for I2C2

impl DMASet<StreamX<DMA1, 3>, 7, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<I2C2>

impl DMASet<StreamX<DMA1, 4>, 0, MemoryToPeripheral> for SPI2

impl DMASet<StreamX<DMA1, 4>, 0, MemoryToPeripheral> for stm32f4xx_hal::spi::Tx<SPI2>

impl DMASet<StreamX<DMA1, 4>, 3, MemoryToPeripheral> for stm32f4xx_hal::i2c::dma::Tx<I2C3>

impl DMASet<StreamX<DMA1, 4>, 3, MemoryToPeripheral> for I2C3

impl DMASet<StreamX<DMA1, 4>, 5, MemoryToPeripheral> for DMAR<TIM3>

impl DMASet<StreamX<DMA1, 4>, 5, MemoryToPeripheral> for CCR1<TIM3>

impl DMASet<StreamX<DMA1, 4>, 5, PeripheralToMemory> for DMAR<TIM3>

impl DMASet<StreamX<DMA1, 4>, 5, PeripheralToMemory> for CCR1<TIM3>

impl DMASet<StreamX<DMA1, 4>, 6, MemoryToPeripheral> for CCR2<TIM5>

impl DMASet<StreamX<DMA1, 4>, 6, PeripheralToMemory> for CCR2<TIM5>

impl DMASet<StreamX<DMA1, 5>, 0, MemoryToPeripheral> for SPI3

impl DMASet<StreamX<DMA1, 5>, 0, MemoryToPeripheral> for stm32f4xx_hal::spi::Tx<SPI3>

impl DMASet<StreamX<DMA1, 5>, 1, PeripheralToMemory> for stm32f4xx_hal::i2c::dma::Rx<I2C1>

impl DMASet<StreamX<DMA1, 5>, 1, PeripheralToMemory> for I2C1

impl DMASet<StreamX<DMA1, 5>, 3, MemoryToPeripheral> for CCR1<TIM2>

impl DMASet<StreamX<DMA1, 5>, 3, PeripheralToMemory> for CCR1<TIM2>

impl DMASet<StreamX<DMA1, 5>, 4, PeripheralToMemory> for USART2

impl DMASet<StreamX<DMA1, 5>, 4, PeripheralToMemory> for stm32f4xx_hal::serial::Rx<USART2>

impl DMASet<StreamX<DMA1, 5>, 5, MemoryToPeripheral> for CCR2<TIM3>

impl DMASet<StreamX<DMA1, 5>, 5, PeripheralToMemory> for CCR2<TIM3>

impl DMASet<StreamX<DMA1, 5>, 6, MemoryToPeripheral> for stm32f4xx_hal::i2c::dma::Tx<I2C3>

impl DMASet<StreamX<DMA1, 5>, 6, MemoryToPeripheral> for I2C3

impl DMASet<StreamX<DMA1, 6>, 1, MemoryToPeripheral> for stm32f4xx_hal::i2c::dma::Tx<I2C1>

impl DMASet<StreamX<DMA1, 6>, 1, MemoryToPeripheral> for I2C1

impl DMASet<StreamX<DMA1, 6>, 2, MemoryToPeripheral> for DMAR<TIM4>

impl DMASet<StreamX<DMA1, 6>, 2, PeripheralToMemory> for DMAR<TIM4>

impl DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral> for CCR2<TIM2>

impl DMASet<StreamX<DMA1, 6>, 3, MemoryToPeripheral> for CCR4<TIM2>

impl DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory> for CCR2<TIM2>

impl DMASet<StreamX<DMA1, 6>, 3, PeripheralToMemory> for CCR4<TIM2>

impl DMASet<StreamX<DMA1, 6>, 4, MemoryToPeripheral> for USART2

impl DMASet<StreamX<DMA1, 6>, 4, MemoryToPeripheral> for stm32f4xx_hal::serial::Tx<USART2>

impl DMASet<StreamX<DMA1, 6>, 6, MemoryToPeripheral> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 6>, 6, PeripheralToMemory> for DMAR<TIM5>

impl DMASet<StreamX<DMA1, 7>, 0, MemoryToPeripheral> for SPI3

impl DMASet<StreamX<DMA1, 7>, 0, MemoryToPeripheral> for stm32f4xx_hal::spi::Tx<SPI3>

impl DMASet<StreamX<DMA1, 7>, 1, MemoryToPeripheral> for stm32f4xx_hal::i2c::dma::Tx<I2C1>

impl DMASet<StreamX<DMA1, 7>, 1, MemoryToPeripheral> for I2C1

impl DMASet<StreamX<DMA1, 7>, 2, MemoryToPeripheral> for CCR3<TIM4>

impl DMASet<StreamX<DMA1, 7>, 2, PeripheralToMemory> for CCR3<TIM4>

impl DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral> for DMAR<TIM2>

impl DMASet<StreamX<DMA1, 7>, 3, MemoryToPeripheral> for CCR4<TIM2>

impl DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory> for DMAR<TIM2>

impl DMASet<StreamX<DMA1, 7>, 3, PeripheralToMemory> for CCR4<TIM2>

impl DMASet<StreamX<DMA1, 7>, 5, MemoryToPeripheral> for CCR3<TIM3>

impl DMASet<StreamX<DMA1, 7>, 5, PeripheralToMemory> for CCR3<TIM3>

impl DMASet<StreamX<DMA1, 7>, 7, MemoryToPeripheral> for stm32f4xx_hal::i2c::dma::Tx<I2C2>

impl DMASet<StreamX<DMA1, 7>, 7, MemoryToPeripheral> for I2C2

impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u16>> for MemoryToMemory<u16>

impl DMASet<StreamX<DMA2, 0>, 0, MemoryToMemory<u32>> for MemoryToMemory<u32>

impl DMASet<StreamX<DMA2, 0>, 0, PeripheralToMemory> for Adc<ADC1>

impl DMASet<StreamX<DMA2, 0>, 0, PeripheralToMemory> for ADC1

impl DMASet<StreamX<DMA2, 0>, 3, PeripheralToMemory> for SPI1

impl DMASet<StreamX<DMA2, 0>, 3, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<SPI1>

impl DMASet<StreamX<DMA2, 0>, 4, PeripheralToMemory> for SPI4

impl DMASet<StreamX<DMA2, 0>, 4, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<SPI4>

impl DMASet<StreamX<DMA2, 0>, 6, MemoryToPeripheral> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 0>, 6, PeripheralToMemory> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u16>> for MemoryToMemory<u16>

impl DMASet<StreamX<DMA2, 1>, 0, MemoryToMemory<u32>> for MemoryToMemory<u32>

impl DMASet<StreamX<DMA2, 1>, 4, MemoryToPeripheral> for SPI4

impl DMASet<StreamX<DMA2, 1>, 4, MemoryToPeripheral> for stm32f4xx_hal::spi::Tx<SPI4>

impl DMASet<StreamX<DMA2, 1>, 5, PeripheralToMemory> for USART6

impl DMASet<StreamX<DMA2, 1>, 5, PeripheralToMemory> for stm32f4xx_hal::serial::Rx<USART6>

impl DMASet<StreamX<DMA2, 1>, 6, MemoryToPeripheral> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 1>, 6, PeripheralToMemory> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u16>> for MemoryToMemory<u16>

impl DMASet<StreamX<DMA2, 2>, 0, MemoryToMemory<u32>> for MemoryToMemory<u32>

impl DMASet<StreamX<DMA2, 2>, 3, PeripheralToMemory> for SPI1

impl DMASet<StreamX<DMA2, 2>, 3, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<SPI1>

impl DMASet<StreamX<DMA2, 2>, 4, PeripheralToMemory> for USART1

impl DMASet<StreamX<DMA2, 2>, 4, PeripheralToMemory> for stm32f4xx_hal::serial::Rx<USART1>

impl DMASet<StreamX<DMA2, 2>, 5, PeripheralToMemory> for USART6

impl DMASet<StreamX<DMA2, 2>, 5, PeripheralToMemory> for stm32f4xx_hal::serial::Rx<USART6>

impl DMASet<StreamX<DMA2, 2>, 6, MemoryToPeripheral> for CCR2<TIM1>

impl DMASet<StreamX<DMA2, 2>, 6, PeripheralToMemory> for CCR2<TIM1>

impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u16>> for MemoryToMemory<u16>

impl DMASet<StreamX<DMA2, 3>, 0, MemoryToMemory<u32>> for MemoryToMemory<u32>

impl DMASet<StreamX<DMA2, 3>, 3, MemoryToPeripheral> for SPI1

impl DMASet<StreamX<DMA2, 3>, 3, MemoryToPeripheral> for stm32f4xx_hal::spi::Tx<SPI1>

impl DMASet<StreamX<DMA2, 3>, 4, MemoryToPeripheral> for SDIO

impl DMASet<StreamX<DMA2, 3>, 4, PeripheralToMemory> for SDIO

impl DMASet<StreamX<DMA2, 3>, 5, PeripheralToMemory> for SPI4

impl DMASet<StreamX<DMA2, 3>, 5, PeripheralToMemory> for stm32f4xx_hal::spi::Rx<SPI4>

impl DMASet<StreamX<DMA2, 3>, 6, MemoryToPeripheral> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 3>, 6, PeripheralToMemory> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u16>> for MemoryToMemory<u16>

impl DMASet<StreamX<DMA2, 4>, 0, MemoryToMemory<u32>> for MemoryToMemory<u32>

impl DMASet<StreamX<DMA2, 4>, 0, PeripheralToMemory> for ADC1

impl DMASet<StreamX<DMA2, 4>, 5, MemoryToPeripheral> for SPI4

impl DMASet<StreamX<DMA2, 4>, 5, MemoryToPeripheral> for stm32f4xx_hal::spi::Tx<SPI4>

impl DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 4>, 6, MemoryToPeripheral> for CCR4<TIM1>

impl DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 4>, 6, PeripheralToMemory> for CCR4<TIM1>

impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u16>> for MemoryToMemory<u16>

impl DMASet<StreamX<DMA2, 5>, 0, MemoryToMemory<u32>> for MemoryToMemory<u32>

impl DMASet<StreamX<DMA2, 5>, 3, MemoryToPeripheral> for SPI1

impl DMASet<StreamX<DMA2, 5>, 3, MemoryToPeripheral> for stm32f4xx_hal::spi::Tx<SPI1>

impl DMASet<StreamX<DMA2, 5>, 4, PeripheralToMemory> for USART1

impl DMASet<StreamX<DMA2, 5>, 4, PeripheralToMemory> for stm32f4xx_hal::serial::Rx<USART1>

impl DMASet<StreamX<DMA2, 5>, 6, MemoryToPeripheral> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 5>, 6, PeripheralToMemory> for DMAR<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u16>> for MemoryToMemory<u16>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToMemory<u32>> for MemoryToMemory<u32>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR2<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, MemoryToPeripheral> for CCR3<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR1<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR2<TIM1>

impl DMASet<StreamX<DMA2, 6>, 0, PeripheralToMemory> for CCR3<TIM1>

impl DMASet<StreamX<DMA2, 6>, 4, MemoryToPeripheral> for SDIO

impl DMASet<StreamX<DMA2, 6>, 4, PeripheralToMemory> for SDIO

impl DMASet<StreamX<DMA2, 6>, 5, MemoryToPeripheral> for USART6

impl DMASet<StreamX<DMA2, 6>, 5, MemoryToPeripheral> for stm32f4xx_hal::serial::Tx<USART6>

impl DMASet<StreamX<DMA2, 6>, 6, MemoryToPeripheral> for CCR3<TIM1>

impl DMASet<StreamX<DMA2, 6>, 6, PeripheralToMemory> for CCR3<TIM1>

impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u8>> for MemoryToMemory<u8>

impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u16>> for MemoryToMemory<u16>

impl DMASet<StreamX<DMA2, 7>, 0, MemoryToMemory<u32>> for MemoryToMemory<u32>

impl DMASet<StreamX<DMA2, 7>, 4, MemoryToPeripheral> for USART1

impl DMASet<StreamX<DMA2, 7>, 4, MemoryToPeripheral> for stm32f4xx_hal::serial::Tx<USART1>

impl DMASet<StreamX<DMA2, 7>, 5, MemoryToPeripheral> for USART6

impl DMASet<StreamX<DMA2, 7>, 5, MemoryToPeripheral> for stm32f4xx_hal::serial::Tx<USART6>